2025 ASEE Annual Conference & Exposition

This paper introduces a course project to simulate a RISC-V CPU using Python as the hardware description language (HDL). Using Python for hardware description is not new. For example, MyHDL is an open-source Python HDL. However, this and other solutions focus on synthesis to produce ASIC and FPGA designs. This imposes added complexity that we do not need to perform behavioral simulation of CPU designs in an undergraduate computer science course. Our approach, in contrast, is minimal, imposing only a few constraints to focus on learning hardware description concepts at the expense of synthesis abilities. By capitalizing on the student's familiarity with Python from other courses, students are able to explore hardware design concepts while avoiding the steep learning curve associated with traditional HDLs. Furthermore, it is easier for students to understand and debug their code because they are already familiar with the syntax. The Python-based HDL is designed to be structurally similar to Verilog. Core Verlog concepts like modules and wires are related to Python classes and functions. This similarity facilitates a smoother transition for students who might go on to use Verilog or another HDL in the future.