2024 ASEE Annual Conference & Exposition

The traditional method of functional verification of digital designs in industry has been simulation.
However, due to increase in design complexity and size, the traditional approach of simulation is
becoming a bottleneck to achieve desired level of coverage and functional correctness. Due to the same
reason, formal verification is becoming one of the widely used methodology for functional verification of
RTL designs in industry. This paper focuses on designing a graduate level course to introduce assertion
based formal verification into the graduate Electrical and Computer Engineering curriculum at Portland
State University (PSU). The course is unique for the application of formal methods using industrial tools.
We describe approaches designed to make students familiar with what, why and where of formal
verification, while designing projects to give them hands on experience with formal verification tools like
VC Formal. Our successful experience demonstrates an effective path of applying industrial formal
method tools in graduate education programs.