2023 ASEE Annual Conference & Exposition

Capstone Project: CPU Design with Multiplexer

Abstract

For a capstone design project, we designed and implemented an 8-bit CPU on an Altera DE2 FPGA board. The CPU uses 4-bit opcodes and can execute 16 instructions, including basic arithmetic and logic operations. We simplified the control unit by implementing it with a multiplexer. We fully tested the CPU by inputting instructions and data through the DE2 board switches, and displaying the results on the seven-segment displays and LEDs. This project provides a valuable opportunity for students majoring in electrical engineering and computer science to gain insight into the relationship between machine codes and their corresponding operations.