2026 ASEE Annual Conference & Exposition

As Artificial Intelligence (AI) becomes integral to modern engineering practice, we explored how generative AI and large language models (LLMs) can enhance digital logic design education. Our senior design project developed a set of lab modules that allow Electrical Engineering students to use LLMs to design, verify, and test digital logic circuits more efficiently. We built an automated workflow that generates Verilog code, simulates designs in Vivado, validates numerical results in MATLAB, and performs hardware-in-the-loop testing on an FPGA board. Four LLMs—ChatGPT, Claude, Gemini v1.5, and LLaMA—were evaluated on various HDL design tasks, including combinational logic, finite-state machines, RISC-V datapaths, and matrix multiplication. We compared AI-assisted results against a traditional workflow using metrics such as design correctness, synthesizability, timing closure, and code quality to assess improvements in productivity, robustness, and usability.