2026 ASEE Annual Conference & Exposition

A RISC-V Soft-Core-Based Embedded Systems Course Using Artix-7 FPGA Platforms

Presented at Electrical and Computer Engineering Division (ECE) Technical Session 6

RISC-V is an open-standard Instruction Set Architecture (ISA) that enables engineers and educators across industries to learn and develop microcontroller and microprocessor architectures for a range of systems, including mobile, laptop, and server applications. A RISC-V soft-core processor can be either a complete or a prototype platform for an embedded computing system. Using FPGA boards, a soft-core RISC-V processor can be studied and learned through hands-on engineering methods. In this paper, the course content and hands-on laboratory examples using RISC-V soft-core systems on an Xilinx Artix-7 FPGA will be introduced. This work is the outcome of the RISC-V embedded system research and development effort, and the authors have found that a custom compact-sized RISC-V soft-core processor can be effectively studied in engineering education through experimentation and hands-on laboratories. This course can be an elective course or a training course for students who have already taken junior-level embedded systems courses or an engineering course for graduate students. It introduces the RISC-V soft-core processor for embedded systems using a Xilinx Artix-7 FPGA. Xilinx provides RISC-V softcore boards. A Xilinx Basys 3 board is a low-cost Artix-7 FPGA board suitable for FPGA education. This paper provides embedded system laboratory examples using an Artix-7 FPGA board, including GPIO and ADC labs. For the laboratories, a Xilinx Artix-7 FPGA board is used with a custom laboratory board. The designed and fabricated custom laboratory kit for the RISC-V board is introduced. This paper presents and discusses the educational values of the RISC-V embedded system.

Authors

Mr. Zhihao Pan http://orcid.org/0000-0002-8051-7979 Texas A&M University [biography]

Zhihao Pan is currently a PhD candidate in the Department of Electrical and Computer Engineering at Texas A&M University in College Station, Texas, USA. He earned his M.S. degree in Engineering Technology and his B.S. degree in Electronic Systems Engineering Technology from Texas A&M University. His research interests include RISC-V processor architecture, embedded systems, FPGA-based design, and hardware security.
Dr. Byul Hur Texas A&M University [biography]

Dr. B. Hur received his B.S. degree in Electronics Engineering from Yonsei University, in Seoul, Korea, in 2000, and his M.S. and Ph.D. degrees in Electrical and Computer Engineering from the University of Florida, Gainesville, FL, USA, in 2007 and 2011, respectively. In 2016, he joined the faculty of Texas A&M University, College Station, TX. USA, where he is currently an Associate Professor. He worked as a postdoctoral associate from 2011 to 2016 at the University Florida previously. His research interests include Mixed-signal/RF circuit design and testing, measurement automation, environmental & biomedical data measurement, and educational robotics development.
Dr. Wei Zhan http://orcid.org/0000-0002-9956-1910 Texas A&M University [biography]

Dr. Wei Zhan is a Professor of Electronic Systems Engineering Technology and Associate Department Head for Undergraduate Studies at Texas A&M University. Dr. Zhan earned his D.Sc. in Systems Science and Mathematics from Washington University in St. Louis in 1991. From 1991 to 1995, he worked at University of California, San Diego and Wayne State University as a postdoctoral researcher and visiting assistant professor, respectively. From 1995 to 2006, he worked in the automotive industry as a system engineer. In 2006 he joined the Electronic Systems Engineering Technology faculty at Texas A&M. Dr. Zhan holds a joint appointment position in the department of Electrical and Computer Engineering at Texas A&M University. He is an American Society for Quality certified Six Sigma Black Belt and an ASQ Fellow. His research activities include control system theory and applications to industry, fault prognosis, system engineering, robust design, modeling, simulation, quality control, and optimization.

Note

The full paper will be available to logged in and registered conference attendees once the conference starts on June 21, 2026, and to all visitors after the conference ends on June 24, 2026

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