2025 ASEE Annual Conference & Exposition

RISC-V System-on-Chip Design Textbook and Course

We wrote a textbook, RISC-V System-on-Chip Design, to bridge the gap between learning about the theory of processor, computer architecture, and system-on-chip (SoC) design and being able to put these theories into practice by understanding, simulating, analyzing, and expanding a fully functional processor and SoC. The book begins with a brief history of processor design and an overview of the RISC-V architecture and then describes the tools needed to work with Wally, the open-source RISC-V SoC described in the book. These tools include GCC and the Sail, Spike, and Verilator simulators as well as best practices in hardware description language (HDL) design, design verification, and logic synthesis. The Wally SoC supports both of RISC-V’s base integer instruction sets, RV32I and RV64I, caches, branch prediction, virtual memory, and many extensions, including the compressed (C), multiply/divide (M), floating-point (Zfh/F/D/Q), atomic (A), and bit manipulation (B) extensions. Wally supports the RVI20U32, RVI20U64, and RVA22S64 RISC-V profiles and can boot Linux with privilege modes and virtual memory and can run on an FPGA. The textbook can be used to teach courses in computer architecture, SoC design, design verification, embedded systems, or a subset of these in theory, practice, or both. We describe two types of courses we taught using a draft version of this textbook: a senior/master’s level course that focused on all stages of SoC design and a second course taught at the sophomore/junior level that focused on computer architecture and processor design only. These courses used the labs, exercises, and Wally SoC that accompany the textbook. We expect this book and course, as well as Wally, to continue to evolve both in its capabilities and in the way that it is used and taught.

Authors

Dr. Rose Thompson Oklahoma State University [biography]

Rose Thompson received her Ph.D. in Electrical Engineering from Oklahoma State University and two B.S. degrees in Electrical Engineering and Computer Engineering from the University of Washington. She has also designed chips at the Air Force Research Laboratory. Her professional interests include SoC design and verification, custom instruction set architectures, branch prediction, memory systems, and secure computing. Rose also enjoys biking, hiking, rock climbing, and playing the piano.
Prof. David L Harris Harvey Mudd College [biography]

David Harris is the Harvey S. Mudd Professor of Engineering Design at Harvey Mudd College. He received his Ph.D. from Stanford University and S.B. and M.Eng. degrees from MIT. His interests are in the area of microprocessor design, computer arithmetic, and high speed and low power circuits. David is the author of Digital Design and Computer Architecture, CMOS VLSI Design, Logical Effort, and Skew-Tolerant Circuit Design, and he holds sixteen patents in the field. He has designed chips at Intel, Broadcom, Sun Microsystems, Hewlett-Packard, and elsewhere. David’s other interests include writing Southern California hiking guidebooks, building experimental aircraft, and traveling with his family.
James Stine Jr. Oklahoma State University [biography]

I am a Professor at Oklahoma State University interested in pushing the frontiers of computation within digital logic for general-purpose and application-specific computer architectures. I have interests in logic design for high-speed and low-power arithmetic, VLSI, FPGA, memory architectures, divide and square root implementations, computer architectures, cryptographic implementations, and graphics applications.

I have also developed several design flows for use with Electronic Design Automation (EDA) tools, including the FreePDK with my colleagues Rhett Davis from NC State University and those at the Semiconductor Research Corporation (SRC), several Cadence Design Systems (CDS) flows including the GPDK and MOSIS flows for use with CDS, National Science Foundation-funded OpenRAM, and Mentor Graphics and Synopsys EDA flows. I have also developed design flows for Google, Skywater Technology, IBM, trusted foundry, and the US Air Force. I am committed to use my experience to help others learn these tools and help develop them to further research endeavors for everyone involved.
Prof. Sarah L Harris http://orcid.org/0000-0002-4777-8130 University of Nevada - Las Vegas [biography]

Sarah L. Harris is a Professor of Electrical and Computer Engineering at the University of Nevada, Las Vegas. She completed her M.S. and Ph.D. at Stanford University. Before joining UNLV in 2014, she was a faculty member at Harvey Mudd College for ten years. She is the co-author of four textbooks, including Digital Design and Computer Architecture: RISC-V Edition (2021, Morgan Kaufmann). Her research interests include computer architecture and applications of embedded systems and machine learning to biomedical engineering and robotics.

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The full paper will be available to logged in and registered conference attendees once the conference starts on June 22, 2025, and to all visitors after the conference ends on June 25, 2025

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