2025 ASEE Annual Conference & Exposition

Design and Organization of a Bring-Up First Vertically-Integrated Chip Design and Fabrication Co-Curricular

Presented at ECE-Career Development and Program Structures

The advent of lower-cost application-specific integrated circuit (ASIC) fabrication through multi-project wafer submissions and open-source synthesis tooling, such as those provided by Efabless, brings a novel opportunity for a vertically-integrated student-led co-curricular based on the design and fabrication of custom ASICs. Based on a bring-up first methodology that emphasizes the hands-on experience of testing and validating physical hardware early in the learning journey, ChipForge encourages students to extend the concepts learned in their existing coursework to practical applications in physical projects. It is the culmination of years of technical and organizational work through two master's students, many senior design teams, a group of freshman honors students, and the first members of the co-curricular. With this co-curricular as a foundation, students integrate information from separate engineering design courses--from digital logic to embedded firmware to microarchitecture development--in each cohesive output product.

This paper presents the technical and organizational infrastructure from which ChipForge was formed as well as results gathered from participating students. Results of this project are presented to evaluate the effectiveness of the co-curricular for improving not only the hard skills of ASIC development but also the soft skills of leadership and group collaboration. By analyzing available evidence, we explore the effects of the documentation, training approach, and co-curricular environment of a vertically-integrated, bring-up first methodology on students' career readiness.

Authors

Gregory Theodore Ling Iowa State University of Science and Technology [biography]

Gregory Ling is a recent graduate from Iowa State University with a Master's degree in Computer Engineering with a focus in Computing and Networking Systems, now working at IBM. He was the primary student lead creating the ChipForge co-curricular on which this paper is based.
Jackson Hafele Iowa State University of Science and Technology [biography]

Jackson Hafele is currently working in industry as a logic design engineer at ForwardEdge ASIC in St. Paul, Minnesota. He completed his B.S. and M.S. in electrical and computer engineering at Iowa State University, with a focus on Computing and Networking Systems in his graduate program.
Dr. Nicholas D. Fila Iowa State University of Science and Technology [biography]

Nicholas D. Fila is an assistant teaching professor in the Department of Electrical and Computer Engineering at Iowa State University. He earned a B.S. in Electrical Engineering and a M.S. in Electrical and Computer Engineering from the University of Illinois-Urbana-Champaign and a Ph.D. in Engineering Education from Purdue University. His research interests include empathy, ethics, design thinking, and course design.
Dr. Henry Duwe http://orcid.org/0000-0003-2310-7399 Iowa State University of Science and Technology [biography]

Henry Duwe received his B.S. degree in computer engineering and computer science from the University of Wisconsin--Madison and his M.S. and Ph.D. in electrical and computer engineering (ECE) from the University of Illinois at Urbana-Champaign (UIUC). He is an Associate Professor in the Electrical and Computer Engineering (ECpE) Department at Iowa State University. His research interests include computer architecture, compilers, design automation, and engineering education. He is focusing on the architecture and design of dependable and intelligent energy-harvesting computer systems. He instigated and advises the Chip Forge chip fabrication co-curricular.

Note

The full paper will be available to logged in and registered conference attendees once the conference starts on June 22, 2025, and to all visitors after the conference ends on June 25, 2025

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