2025 ASEE Annual Conference & Exposition

An FPGA-based Toolchain for Computer Architecture Courses

Presented at Computers in Education Division (COED) Track 3.A

Computer architecture (CA) courses are often challenging for students in computer science and engineering disciplines, particularly at the intersection of hardware and software. Concepts like instruction set architecture, registers, and memory operations are typically taught through assembly programming and simulation, while hardware elements such as ALUs, registers, and pipelines are introduced in separate, often isolated, chapters. This fragmented approach can lead students to perceive CA as two distinct subjects: one focusing on assembly language programming and the other on processor hardware design.

This divide creates a disconnect between disciplines—computer science students tend to focus more on software aspects, while electrical and computer engineering students gravitate towards hardware. As a result, neither group fully appreciates the critical interplay between hardware and software in modern processor design.

To address this gap, we propose an FPGA-based toolkit that enhances the learning experience in CA courses by demonstrating how hardware supports software execution. Our toolkit implements the RISC-V Integer ISA RV32I processor using Intel Quartus Prime Lite, with built-in FPGA RAM used to store machine code and data. Students can explore two execution options: downloading the processor design to an actual Intel FPGA and viewing the results on an LCD, or simulating the program using ModelSim, a tool included in the Quartus software package.

In addition to running assembly programs, the toolkit allows students to experiment with advanced features such as caching, dynamic branch prediction, multi-core CPUs, and out-of-order execution. The toolkit is suitable for both introductory and advanced CA courses, providing hands-on experience that deepens students' understanding of hardware-software integration.

Long term, incorporating this tool into CA courses has the potential to bridge the gap between software and hardware understanding, inspire greater student interest in processor design, and open up new career opportunities in this field.

Authors
  1. Kevin Garcia-Estala The University of Tulsa [biography]
  2. Issai Gutierrez The University of Tulsa [biography]
Note

The full paper will be available to logged in and registered conference attendees once the conference starts on June 22, 2025, and to all visitors after the conference ends on June 25, 2025