2024 ASEE Annual Conference & Exposition

Improving Verification Skills for a Discrete-Event Simulation Model

Presented at Industrial Engineering Division (IND) Technical Session 3

For over two decades of teaching discrete-event simulation courses, a consistent problem has been noted: most students lack adequate skills needed to verify their simulation models. Compounding this issue is the confusion many students have regarding the distinction between debugging and verification. Most often, professional versions of simulation software, adept at running models and producing output, overlook logical errors. This can lead students to mistakenly believe their models are flawless. Additionally, some students rely solely on animation of their models for verification, which, though helpful, cannot provide the precise and dependable information necessary for a thorough verification process. Unfortunately, existing textbooks and literature often provide limited discussion on model verification, leaving students inadequately prepared.

This paper introduces a set of comprehensive guidelines designed to facilitate the systematic verification of simulation models. To illustrate the practical application of these guidelines, the paper showcases examples. By following these guidelines, students can refine their verification skills and achieve more reliable models, moreover develop critical thinking abilities throughout the process.

This paper also proposes a special-purpose flowchart called a "Logical Model." This model serves a valuable role throughout the simulation process, including: initial system study, model creation, semantic debugging, and verification. The discussion on additional applications of the Logical Model, such as analysis and design of experiments, will be presented in a later paper.

Authors
  1. Dr. Sima Parisay California State Polytechnic University, Pomona [biography]
Download paper (4.28 MB)

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